philips semiconductors product specification trenchmos ? transistor buk9540-100a logic level fet BUK9640-100a general description quick reference data n-channel enhancement mode logic symbol parameter max. unit level field-effect power transistor in a plastic envelope available in v ds drain-source voltage 100 v to220ab and sot404 . using i d drain current (dc) 37 a ' trench ' technology which features p tot total power dissipation 138 w very low on-state resistance. it is t j junction temperature 175 ?c intended for use in automotive and r ds(on) drain-source on-state general purpose switching resistance v gs = 5 v 40 m w applications. v gs = 10 v 39 m w pinning to220ab & sot404 pin configuration symbol pin description 1 gate 2 drain 3 source tab/mb drain limiting values limiting values in accordance with the absolute maximum system (iec 134) symbol parameter conditions min. max. unit v ds drain-source voltage - - 100 v v dgr drain-gate voltage r gs = 20 k w - 100 v v gs gate-source voltage - - 10 v v gsm non-repetitive gate-source voltage t p 50 m s - 15 v i d drain current (dc) t mb = 25 ?c - 37 a i d drain current (dc) t mb = 100 ?c - 26 a i dm drain current (pulse peak value) t mb = 25 ?c - 149 a p tot total power dissipation t mb = 25 ?c - 138 w t stg , t j storage & operating temperature - - 55 175 ?c thermal resistances symbol parameter conditions typ. max. unit r th j-mb thermal resistance junction to - - 1.1 k/w mounting base r th j-a thermal resistance junction to in free air 60 - k/w ambient(to220ab) r th j-a thermal resistance junction to minimum footprint, fr4 50 - k/w ambient(sot404) board 123 tab 13 mb 2 sot404 to220ab d g s december 1999 1 rev 1.000
philips semiconductors product specification trenchmos ? transistor buk9540-100a logic level fet BUK9640-100a static characteristics t j = 25?c unless otherwise specified symbol parameter conditions min. typ. max. unit v (br)dss drain-source breakdown v gs = 0 v; i d = 0.25 ma; 100 - - v voltage t j = -55?c 89 - - v v gs(to) gate threshold voltage v ds = v gs ; i d = 1 ma 1 1.5 2.0 v t j = 175?c 0.5 - - v t j = -55?c - - 2.3 v i dss zero gate voltage drain current v ds = 100 v; v gs = 0 v; - 0.05 10 m a t j = 175?c - - 500 m a i gss gate source leakage current v gs = 10 v; v ds = 0 v - 2 100 na r ds(on) drain-source on-state v gs = 5 v; i d = 25 a - 30 40 m w resistance t j = 175?c - - 100 m w v gs = 10 v; i d = 25 a - 29 39 m w v gs = 4.5 v; i d = 25 a - 31 43 m w dynamic characteristics t mb = 25?c unless otherwise specified symbol parameter conditions min. typ. max. unit c iss input capacitance v gs = 0 v; v ds = 25 v; f = 1 mhz - 2304 3072 pf c oss output capacitance - 222 266 pf c rss feedback capacitance - 151 207 pf t d on turn-on delay time v dd = 30 v; r load =1.2 w ; - 20 30 ns t r turn-on rise time v gs = 5 v; r g = 10 w - 135 189 ns t d off turn-off delay time - 125 189 ns t f turn-off fall time - 90 135 ns l d internal drain inductance measured from drain lead 6 mm - 4.5 - nh from package to centre of die l d internal drain inductance measured from contact screw on - 3.5 - nh tab to centre of die(to220ab) l d internal drain inductance measured from upper edge of drain - 2.5 - nh tab to centre of die(sot404) l s internal source inductance measured from source lead to - 7.5 - nh source bond pad reverse diode limiting values and characteristics t j = 25?c unless otherwise specified symbol parameter conditions min. typ. max. unit i dr continuous reverse drain - - 37 a current i drm pulsed reverse drain current - - 149 a v sd diode forward voltage i f = 25 a; v gs = 0 v - 0.85 1.2 v i f = 37 a; v gs = 0 v - 1.1 - v t rr reverse recovery time i f = 37 a; -di f /dt = 100 a/ m s; - 60 - ns q rr reverse recovery charge v gs = -10 v; v r = 30 v - 0.24 - m c december 1999 2 rev 1.000
philips semiconductors product specification trenchmos ? transistor buk9540-100a logic level fet BUK9640-100a avalanche limiting value symbol parameter conditions min. typ. max. unit w dss 1 drain-source non-repetitive i d = 25 a; v dd 25 v; - - 31 mj unclamped inductive turn-off v gs = 5 v; r gs = 50 w ; t mb = 25 ?c energy fig.1. normalised power dissipation. pd% = 100 p d /p d 25 ?c = f(t mb ) fig.2. normalised continuous drain current. id% = 100 i d /i d 25 ?c = f(t mb ); conditions: v gs 3 5 v fig.3. safe operating area. t mb = 25 ?c i d & i dm = f(v ds ); i dm single pulse; parameter t p fig.4. transient thermal impedance. z th j-mb = f(t); parameter d = t p /t 0 20 40 60 80 100 120 140 160 180 tmb / c pd% normalised power derating 120 110 100 90 80 70 60 50 40 30 20 10 0 1 1 10 100 1000 id/a 10 100 1000 rds(on)=vds/id dc 10us 100us 100ms 10ms 1ms tp = vds/v 1us 0 20 40 60 80 100 120 140 160 180 tmb / c id% normalised current derating 120 110 100 90 80 70 60 50 40 30 20 10 0 0.001 0.01 0.1 1 10 1e-07 1e-05 1e-03 1e-01 1e+01 t/s zth/(k/w) 0 0.02 0.05 0.1 0.2 0.5 1 for maximum permissible repetive avanche current see fig.18. december 1999 3 rev 1.000
philips semiconductors product specification trenchmos ? transistor buk9540-100a logic level fet BUK9640-100a fig.5. typical output characteristics, t j = 25 ?c . i d = f(v ds ); parameter v gs fig.6. typical on-state resistance, t j = 25 ?c . r ds(on) = f(i d ); parameter v gs fig.7. typical on-state resistance, t j = 25 ?c . r ds(on) = f(v gs ); conditions: i d = 25 a; fig.8. typical transfer characteristics. i d = f(v gs ) ; conditions: v ds = 25 v; parameter t j fig.9. typical transconductance, t j = 25 ?c . g fs = f(i d ); conditions: v ds = 25 v fig.10. normalised drain-source on-state resistance. a = r ds(on) /r ds(on)25 ?c = f(t j ); i d = 25 a; v gs = 5 v 0 20 40 60 80 100 120 0246810 vds/v id/a 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8 4.0 5.0 10.0 vgs/v = 0 5 10 15 20 25 30 35 40 012345678910 gate-source voltage, vgs (v) drain current, id (a) vds > id x rds(on) tj = 25 c 175 c 20 25 30 35 40 45 50 10 20 30 40 50 60 70 vds/v id/a 3.0 3.2 3.4 3.6 4.0 5.0 0 10 20 30 40 50 60 70 0 10203040 id/a gfs/s 26 28 30 32 34 36 38 345678910 vgs/v rds(on) ohm 0.5 1 1.5 2 2.5 3 -100 -50 0 50 100 150 200 tmb / degc a rds(on) normalised to 25degc december 1999 4 rev 1.000
philips semiconductors product specification trenchmos ? transistor buk9540-100a logic level fet BUK9640-100a fig.11. gate threshold voltage. v gs(to) = f(t j ); conditions: i d = 1 ma; v ds = v gs fig.12. sub-threshold drain current. i d = f(v gs) ; conditions: t j = 25 ?c; v ds = v gs fig.13. typical capacitances, c iss , c oss , c rss . c = f(v ds ); conditions: v gs = 0 v; f = 1 mhz fig.14. typical turn-on gate-charge characteristics. v gs = f(q g ); conditions: i d = 25 a; parameter v ds fig.15. typical reverse diode current. i f = f(v sds ); conditions: v gs = 0 v; parameter t j fig.16. normalised avalanche energy rating. w dss % = f(t mb ); conditions: i d = 75 a -100 -50 0 50 100 150 200 0 0.5 1 1.5 2 2.5 tj / c vgs(to) / v max. typ. min. 0 1 2 3 4 5 0 1020304050 qg / nc vgs / v vds = 14v vds = 44v 0 0.5 1 1.5 2 2.5 3 1e-05 1e-05 1e-04 1e-03 1e-02 1e-01 sub-threshold conduction 2% typ 98% 0 5 10 15 20 25 30 35 40 45 50 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 1.1 1.2 1.3 1.4 1.5 source-drain voltage, vsds (v) source-drain diode current, if (a) tj = 25 c 175 c vgs = 0 v 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 0.01 0.1 1 10 100 vds/v capacitance/nf ciss coss crss 20 40 60 80 100 120 140 160 180 tmb / c 120 110 100 90 80 70 60 50 40 30 20 10 0 wdss% december 1999 5 rev 1.000
philips semiconductors product specification trenchmos ? transistor buk9540-100a logic level fet BUK9640-100a fig.17. avalanche energy test circuit. fig.18. maximum permissible repetitive avalanche current(i av ) versus avalanche time(t av ) for unclamped inductive loads. fig.19. switching test circuit. l t.u.t. vdd rgs r 01 vds -id/100 + - shunt vgs 0 rd t.u.t. vdd rg vds + - vgs 0 w dss = 0.5 li d 2 bv dss /( bv dss - v dd ) 1 10 100 0.001 0.01 0.1 1 10 avalanche time, t av (ms) i av tj prior to avanche 150oc 25oc december 1999 6 rev 1.000
philips semiconductors product specification trenchmos ? transistor buk9540-100a logic level fet BUK9640-100a mechanical data dimensions in mm net mass: 2 g fig.20. sot78 (to220ab); pin 2 connected to mounting base. notes 1. observe the general handling precautions for electrostatic-discharge sensitive devices (esds) to prevent damage to mos gate oxide. 2. refer to mounting instructions for sot78 (to220) envelopes. 3. epoxy meets ul94 v0 at 1/8". 10,3 max 3,7 2,8 3,0 3,0 max not tinned 1,3 max (2x) 123 2,4 0,6 4,5 max 5,9 min 15,8 max 1,3 2,54 2,54 0,9 max (3x) 13,5 min december 1999 7 rev 1.000
philips semiconductors product specification trenchmos ? transistor buk9540-100a logic level fet BUK9640-100a mechanical data fig.21. sot404 surface mounting package. centre pin connected to mounting base. notes 1. this product is supplied in anti-static packaging. the gate-source input must be protected against static discharge during transport or handling. 2. refer to smd footprint design and soldering guidelines, data handbook sc18. 3. epoxy meets ul94 v0 at 1/8". unit a references outline version european projection issue date iec jedec eiaj mm a 1 d 1 d max. e el p h d q c 2.54 2.60 2.20 15.40 14.80 2.90 2.10 11 1.60 1.20 10.30 9.70 4.50 4.10 1.40 1.27 0.85 0.60 0.64 0.46 b dimensions (mm are the original dimensions) sot404 0 2.5 5 mm scale plastic single-ended surface mounted package (philips version of d 2 -pak); 3 leads (one lead cropped) sot404 e e e b d 1 h d d q l p c a 1 a 13 2 mounting base 98-12-14 99-06-25 december 1999 8 rev 1.000
philips semiconductors product specification trenchmos ? transistor buk9540-100a logic level fet BUK9640-100a mounting instructions dimensions in mm fig.22. sot404 : soldering pattern for surface mounting . definitions data sheet status objective specification this data sheet contains target or goal specifications for product development. preliminary specification this data sheet contains preliminary data; supplementary data may be published later. product specification this data sheet contains final product specifications. limiting values limiting values are given in accordance with the absolute maximum rating system (iec 134). stress above one or more of the limiting values may cause permanent damage to the device. these are stress ratings only and operation of the device at these or at any other conditions above those given in the characteristics sections of this specification is not implied. exposure to limiting values for extended periods may affect device reliability. application information where application information is given, it is advisory and does not form part of the specification. philips electronics n.v. 1999 all rights are reserved. reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. the information presented in this document does not form part of any quotation or contract, it is believed to be accurate and reliable and may be changed without notice. no liability will be accepted by the publisher for any consequence of its use. publication thereof does not convey nor imply any license under patent or other industrial or intellectual property rights. life support applications these products are not designed for use in life support appliances, devices or systems where malfunction of these products can be reasonably expected to result in personal injury. philips customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify philips for any damages resulting from such improper use or sale. 17.5 11.5 9.0 5.08 3.8 2.0 december 1999 9 rev 1.000
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